Current-mode electronically tunable universal filter using only plus-type current controlled conveyors and grounded capacitors

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions-all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters omega(o) and omega(o)/Q. No element matching conditions are imposed. Both its active and passive sensitivities are low

Unity / variable gain voltage - mode / current - mode first - order all - pass filters using single Dual - X second generation current conveyor

In this paper, two new general topologies for realizing voltage-mode (VM)/current-mode (CM) first-order all-pass filter transfer functions (TFs) are presented. The proposed topologies use single dual-X second-generation current conveyor (DXCCII) and three impedances Z(1), Z(2) and Z(3). Based on the selection of Z(1), Z(2) and Z(3), new VM and CM all-pass filters with unity or variable gains are obtained. The proposed VM/CM filters have high-input/high-output impedances which provide easy cascading at their input/output terminals, respectively. Non-ideal gain and parasitic impedance effects, associated with actual DXCCII implementation, on the performance of the developed topologies are also included. Finally, simulation program with integrated circuit emphasis (SPICE) simulation results based on level 49, 0.25 mu m TSMC complementary metal-oxide-semiconductor (CMOS) technology parameters are given to confirm the theory

Guest editorial: special issue on signal processing

It affords us great pleasure to introduce you to a collection of the best 10 invited papers focusing on different areas of signal processing that were originally mainly submitted by young scientists and Ph.D. students and, on a limited scale, presented at the 2011 34th International Conference on Telecommunications and Signal Processing (TSP) held on 18-20 August, 2011, in Budapest, Hungary. Here you can find their extended versions, in which the authors present their research results in more depth and detail. [...

Guest editorial: special issue on signal processing

It affords us great pleasure to introduce you to a collection of the best 10 invited papers focusing on different areas of signal processing that were originally mainly submitted by young scientists and Ph.D. students and, on a limited scale, presented at the 2011 34th International Conference on Telecommunications and Signal Processing (TSP) held on 18-20 August, 2011, in Budapest, Hungary. Here you can find their extended versions, in which the authors present their research results in more depth and detail. [...

A low-power multilevel CMOS classifier circuit

İnsanların günlük yaşamında belirli bir sesi, görüntüyü veya analog bir veriyi tanımak için kullandıkları kuralları tanımlamak oldukça karmaşık bir dizi işlem gerektirmektedir ve hatta bu kuralları tanımlamak bazen mümkün olamamaktadır. Oysa pratikte karşılaşılan örüntü tanıma olaylarını, yazılım ve donanım tabanlı tanıma uygulamalarında belirli kriterlere oturtmak mümkündür. Sınıflandırma yöntemleri ilk olarak örüntü sınıflandırma adı altında görülmeye başlanmış ve ilk algoritmalarda basit yapılar ele alınmıştır; ilk gerçeklenen yapıda en yakın komşu yakınsaması kullanılmıştır. Sınıflandırma işlemi, benzer özellik taşıyan objelerin başka farklı özellikte olanlardan ayırt edilmesi şeklinde tanımlanabilir ve otomatik hedef belirleme, yapay zekâ, yapay sinir ağları, analog-sayısal dönüştürücüler, kuantalama, tıbbi tanı, istatistik gibi çeşitli alanlarda kullanılır. Dolaysıyla da, günümüzde, gerek gerçek dünyada gerekse sayısal dünyada verilerin sınıflandırılması büyük önem taşımaktadır. Bugüne kadar sınıflandırma işlemi genellikle çeşitli algoritmalar yardımıyla yazılımsal olarak yapılmaktaydı, oysa birçok uygulamada, sınıflandırma işlemini daha hızlı ve gerçek zamanda yapmak gerektiğinden bu algoritmaların donanımsal olarak gerçeklenmeleri çok daha yararlı olmaktadır. Ayrıca günümüzde portatif cihazların da artmasından dolayı donanımsal olarak gerçeklenecek cihazlarda da güç tüketimi büyük önem kazanmıştır. Dolayısıyla sınıflandırıcı devrelerin de bu ihtiyaçları karşılayacak şekilde tasarlanması gerekmektedir. Bu makalede akım-modlu düşük güçte çalışan bir sınıflandırıcı devresi sunulmaktadır. Önerilen sınıflandırıcı devresi, temel bir bloktan yararlanmaktadır; bu temel bloklar kullanılarak daha gelişmiş sınıflandırıcı yapılarının gerçekleştirilebileceği gösterilmiştir. Önerilen devrenin benzetimleri için 0.35 μm AMS CMOS teknoloji parametreleri kullanılmıştır. Ayrıca çekirdek devre adı verilen temel bloğun, tek boyutlu ve iki boyutlu sınıflandırıcı yapılarının benzetim sonuçları verilmiştir.In the everyday life of humans, to define the rules used to recognize a certain sound, image or an analog data necessitates a sequence of complex processes which sometimes becomes impossible to accomplish. However, to develop well defined software and hardware based criteria in the application of pattern recognition problems, is possible. The aim of classification can be defined as to assign an unknown object to a class containing similar objects (or to distinguish objects having the same properties from those not possessing). Classification is especially important in the real world applications or in the digital world. Basic classification methods using nearest neighbourhood algorithm have first been seen in early sixties under the subject tile" pattern recognition." Classification is used in a huge variety of applications such as automatic target identification, artificial neural networks, artificial intelligence, template matching, pattern recognition, analog to digital converters, quantization, medical diagnosis, statistics etc. Therefore nowadays, be it in the real or digital world, data classification is becoming increasingly important. But until recently, major work on classification was on developing algorithms used in software packages whereas, in many applications it is becoming more and more important to classify data much faster and in real time, entailing the need for hardware realization of these algorithms. Software approaches are not practical for real time applications, the processing is computationally very expensive, consuming a lot of Central Processing Unit (CPU) time when implemented as software running on general purpose computers. So in literature hardware implementation of classifier topologies become necessary. Also in literature hardware realized classifiers which are designed to work in low power operation; moreover some of these hardware classifiers do not have custom tunability. So they can only be used for a specific application. The recent developments in electronics technology has created a perfect medium for the hardware realization of classifier structures which, in turn, will render many classifier application prospects feasible in real time. This paper targets the design and application to real world problems of tunable, low power new classifier circuits using CMOS technology. So, a low-power CMOS implementation of a multi-input data classifier with several output levels is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. An architecture is developed comprising a threshold circuit based on CMOS transistors operating in subthreshold region. To this purpose a one dimensional classifier, called core circuit is proposed. The core circuit also works as a one-dimensional classifier. As this circuit is designed to operate in currentmode the input and the output data is provided to the core circuit with currents. So by interconnecting several core circuits and adding the output currents a multi output classifier can be obtained. Also, combining several core circuits in groups in such a way that each group has identical input current (different from the others), a multi-dimensional, multi-level output classifier can be obtained. Also, numerous efforts in balancing the trade off between power consumption, area and speed have resulted in an acceptable performance. On the other hand, the rapid increasing use of battery operated portable equipment in application areas such as telecommunications and medical electronics increases the importance of low-power and small sized VLSI circuits' technologies. One solution to achieve lowpower and acceptable performance is to operate the transistors in the subthreshold region. The CMOS transistors working in subthreshold region are suitable only for specific applications which need, not very high performance, but low power consumption. The primary aim of this paper is to develop a low power classifier circuit with n inputs and externally tunable decision regions with different output amplitude for each region. Due to the subthreshold operation of the transistors in the proposed core circuit, very low power consumption becomes possible. The proposed core circuit is constructed with two threshold and a subtractor circuit. The SPICE simulation of the threshold circuit, core circuit, one dimensional and two dimensional classifier circuits are given. Using 0.35 μm parameters of AMS CMOS technology, SPICE simulations are performed and a low-power, custom tunable classifier circuit is realized. Because of the parallel processing characteristic of the circuit, it is well suited for real-world applications

New high performance realizations for current controlled conveyor (CCCII)

In this paper two new realizations, one CMOS and one bipolar, for current-controlled conveyor (CCCII) are proposed. The proposed circuits provide a good linearity, very high input impedance at port-y, high output impedance at port-z and good output/input current gain. SPICE simulation results using TUBITAK 3 CMOS process model are included to verify the expected values

All-pass section with high gain opportunity

Minaei, Shahram (Dogus Author) -- Conference full title: 33rd International Conference on Telecommunications and Signal Processing, TSP 2010; Baden near Vienna; Austria; 17 August 2010 through 20 August 2010 -- Paper published in Radioengineering, 20 (1) pp. 3-9. Fultext accessible via https://hdl.handle.net/11376/1383In this paper, a new circuit configuration for realizing voltage-mode (VM) all-pass section (APS) is presented. The circuit is cascadable with other VM circuits because of its high input and low output impedances. It consists of two differential difference current conveyors (DDCCs), one grounded resistor and one grounded capacitor. The proposed circuit can be slightly changed by using two additional grounded resistors to provide high gain. Moreover, a quadrature oscillator with minimum number of active and passive elements is derived from the proposed APS. SPICE simulations are performed to verify the theory.Motorol

CMOS realization of a quantized-output classifier circuit

In this paper a CMOS implementation of a multi-input data classifier with several output levels and a different architecture is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. The classifier circuit’s new architecture consists of the interconnections of core cells each possessing a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using 0.35µm TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results

High swing CMOS realization for third generation current conveyor (CCIII)

In this paper a new CMOS realization for third generation current conveyor (CCIII) is proposed. The proposed circuit provides high swing range at terminals X and Y. The circuit has low input impedances at terminals X and Y and high output impedance at terminals Z+ and Z-. The circuit has 180MHz -3dB cutoff frequency in voltage follower mode. SPICE simulation results using MIETEC 1.2 CMOS process model are given

ASD: çok amaçlı ayarlanabilir sınıflandırıcı devreler

Göknar, İzzet Cem (Dogus Author) -- Minaei, Shahram (Dogus Author) -- Yıldız, Merih (Dogus Author)Çalışmada, ayarlanabilir sınıflandırıcı devreleri ve uygulama alanları incelenmiştir. AMS 0.35 μm CMOS prosesi ile, tasarlanan sınıflandırıcı bir tümdevrenin üretimi de yapılmıştır. Bu sınıflandırıcı devresinin kontrol parametrelerinin bulunmasını sağlayan öğrenme algoritmaları çeşitli uygulamalar için geliştirilmiştir. Sınıflandırma işlemleri geliştirilen algoritmalar ve üretilen devre ile İris ve Haberman veri kümelerine uygulanarak sonuçların uyum içinde olduğu gösterilmiştir.TÜBİTA